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STL6NM60N
N-channel 600 V - 0.85 - 5.75 A - PowerFLATTM (5x5) ultra low gate charge MDmeshTM II Power MOSFET
Features
Type STL6NM60N VDSS @ TJMAX 650 V RDS(on) Max < 0.92 ID 5.75 A(1)
1. The value is rated according Rthj-case
100% avalanche tested Low input capacitance and gate charge Low gate input resistance PowerFLAT (5x5)
Application
Switching applications Figure 1. Internal schematic diagram
Description
This series of devices implements the second generation of MDmeshTM Technology. This revolutionary Power MOSFET associates a new vertical structure to the Company's strip layout to yield one of the world's lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters.
Table 1.
Device summary
Marking L6NM60N Package PowerFLATTM (5x5) Packaging Tape & reel
Order code STL6NM60N
November 2007
Rev 3
1/12
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Contents
STL6NM60N
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................. 6
3 4 5
Test circuit
................................................ 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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STL6NM60N
Electrical ratings
1
Electrical ratings
Table 2.
Symbol VDS VGS ID(1) ID (1) IDM
(1),(2) (3) (3)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25 C (steady state) Drain current (continuous) at TC=100 C Drain current (pulsed) Drain current (continuous) at TC = 25 C Drain current (continuous) at TC=100 C Drain current (pulsed) Total dissipation at TC = 25 C (steady state) Total dissipation at TC = 25 C (steady state) Derating factor
(3)
Value 600 25 5.75 3.62 23 1 0.65 4 2.1 70 0.02 5 -55 to 150
Unit V V A A A A A A W W W/C V/ns C
ID ID
IDM(2), (3) PTOT
(3)
PTOT(1) dv/dt (4) TJ Tstg
Peak diode recovery voltage slope Operating junction temperature storage temperature
1. The value is rated according Rthj-case 2. Pulse width limited by safe operating area. 3. When mounted on FR-4 board of 1inch, 2oz Cu 4. ISD 4.6A, dv/dt 400A/s, VDD = 80%V(BR)DSS
Table 3.
Symbol Rthj-case Rthj-pcb
(1)
Thermal resistance
Parameter Thermal resistance junction-case Thermal resistance junction-pcb Typ -31.2 Max 1.8 58.5 Unit C/W C/W
1. When mounted on FR-4 board of 1inch, 2oz Cu, t < 10 sec
Table 4.
Symbol IAS EAS
Avalanche characteristics
Parameter Avalanche current, repetitive or not-repetitive Single pulse avalanche energy (2)
(1)
Typ 2 65
Unit A mJ
1. Pulse width limited by Tjmax 2. Starting Tj = 25 C, ID= IAS, VDD = 50 V
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Electrical characteristics
STL6NM60N
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 5.
Symbol V(BR)DSS dv/dt (1)
On/off states
Parameter Drain-source breakdown voltage Drain-source voltage slope Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 1 mA, VGS= 0 VDD= 480 V, VGS = 10 V, ID = 4.6 A VDS = Max rating, VDS = Max rating @125 C VGS = 20 V VDS= VGS, ID = 250 A VGS= 10 V, ID= 2.3 A 2 3 0.85 Min. 600 40 1 100
100
Typ.
Max.
Unit V V/ns A A nA V
IDSS IGSS VGS(th) RDS(on)
1.
4 0.92
Characteristics value at turn off on inductive load
Table 6.
Symbol gfs (1) Ciss Coss Crss Coss eq.
(2)
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Output equivalent capacitance Test conditions VDS =15 V, ID = 2.3 A Min. Typ. 4 420 30 4 Max. Unit S pF pF pF
VDS =50V, f=1 MHz, VGS=0
VGS =0, VDS =0 to 480 V f=1 MHz Gate DC Bias=0 test signal level = 20 mV open drain VDD= 480 V, ID = 4.6 A VGS =10 V (see Figure 15)
70
pF
Rg Qg Qgs Qgd
Gate input resistance
6
Total gate charge Gate-source charge Gate-drain charge
13 2 7
nC nC nC
1. Pulsed: pulse duration= 300 s, duty cycle 1.5% 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS
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STL6NM60N
Electrical characteristics
Table 7.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD= 300 V, ID = 2.3 A, RG= 4.7 , VGS = 10 V (see Figure 14) Min. Typ. 10 8 40 9 Max. Unit ns ns ns ns
Table 8.
Symbol ISD
Source drain diode
Parameter Source-drain current Test conditions Min Typ. Max 1 4 ISD= 4.6 A, VGS=0 ISD= 4.6 A, di/dt = 100 A/s, VDD=20 V (see Figure 16) ISD= 4.6 A, di/dt = 100 A/s, VDD=20 V, Tj= 150 C (see Figure 16) 300 2 12 1.3 Unit A A V ns nC A
ISDM (1),(2) Source-drain current (pulsed) VSD(3) trr Qrr IRRM trr Qrr IRRM Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current
Reverse recovery time Reverse recovery charge Reverse recovery current
470 3 12
ns nC A
1. Pulse width limited by safe operating area 2. When mounted on FR-4 board of 1inch, 2oz Cu 3. Pulsed: pulse duration=300s, duty cycle 1.5%
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Electrical characteristics
STL6NM60N
2.1
Figure 2.
Electrical characteristics (curves)
Safe operating area Figure 3. Thermal impedance
Figure 4.
Output characteristics
Figure 5.
Transfer characteristics
Figure 6.
Transconductance
Figure 7.
Static drain-source on resistance
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STL6NM60N Figure 8. Gate charge vs gate-source voltage Figure 9.
Electrical characteristics Capacitance variations
Figure 10. Normalized gate threshold voltage vs temperature
Figure 11. Normalized on resistance vs temperature
Figure 12. Source-drain diode forward characteristics
Figure 13. Normalized BVDSS vs temperature
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Test circuit
STL6NM60N
3
Test circuit
Figure 15. Gate charge test circuit
Figure 14. Switching times test circuit for resistive load
Figure 16. Test circuit for inductive load Figure 17. Unclamped inductive load test switching and diode recovery times circuit
Figure 18. Unclamped inductive waveform
Figure 19. Switching time waveform
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STL6NM60N
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
STL6NM60N
PowerFLATTM(5x5) MECHANICAL DATA
mm. DIM. MIN. A A1 A3 b c D E E2 e 2.49 0.43 0.64 0.80 TYP 0.90 0.02 0.24 0.51 0.71 5.00 5.00 2.57 1.27 2.64 0.01 0.58 0.79 0.016 0.025 MAX. 1.00 0.05 MIN. 0.031 TYP. 0.035 0.0007 0.009 0.020 0.027 0.19 0.19 0.10 0.05 0.103 0.022 0.031 MAX. 0.039 0.002 inch
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STL6NM60N
Revision history
5
Revision history
Table 9.
Date 04-May-2007 23-May-2007 27-Nov-2007
Document revision history
Revision 1 2 3 First release Update test conditions on Table 7 Mechanical data has been updated Changes
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STL6NM60N
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